The use of computer aided design (CAD) tools in the development of complex digital circuit designs is firmly established in the semiconductor industry. Without CAD tools, it would simply be impossible to manage the myriad of connections in a design having well in excess of one million transistors.
CAD tools have other specific advantages. For instance, most CAD tools allow designers to specify a design in terms of its function in an intuitive syntax. This syntax is often referred to as a high level design synthesis language (HDL), or simply a high level language. Statements written in such a language are similar to statements written in common high level computer programming languages, such as BASIC, C, C++, FORTRAN, etc. Also, the operation of circuits described in a high level language can be readily simulated by a computer to test their proper operation prior to manufacture. In the case of a simulation, a series of input bits, or "test vectors" is applied to the simulator. The simulator generates output bits, or "output vectors" which are compared to expected results. Later, an automatic logic synthesizer will convert the high level language code into a specific combination of gates and latches that performs the same function as does the high level language code. This methodology removes many opportunities for error from human hands. It should be noted that there is typically very little resemblance between the high level and low level representations of a design. This dissimilarity makes it very difficult if not impossible to associate high level and low level signals.
Static timing tools are specific CAD tools that identify paths, or connections of nodes, in a design through which a signal propagates with some computed delay. Static timing tools parse the gate level representation of a circuit and estimate the propagation time through every possible path. Typically, static timing programs operate best on circuits expressed at a low level of detail. Conceptually, there is no prohibition against the operation of static timing programs on high level language descriptions of electrical circuits. Designers have empirically discovered that the maximum speed of a circuit may be disproportionately increased by careful attention to a small subset of electrical paths in the circuit. Once identified, these critical "speed paths" can be redesigned to perform better.
"False paths" complicate the use of timing tools. False paths are timing paths that can never be exercised during normal operation of a circuit. Other design constraints often make it impossible for a particular path to fire in a particular way. However, current design and test methodologies make it difficult to associate a speed path with any set of vectors that would exercise the path. Therefore, it is difficult for a human to evaluate whether a path is false or not. Furthermore, the complexity of most designs makes it computationally difficult to determine if a path is false or not. Therefore, it is difficult even for an automated process executing on a computer to identify a false path.
In general, it is very difficult to associate a test vector with the exercise of any particular path in a complex design. This complexity arises whether the path is a speed path or otherwise. Consequently, designers frequently chose to apply millions of test vectors to a model and later to the actual circuit to test the design's proper operation. Such an approach is both inefficient and non-deterministic.
It may be desirable to monitor the propagation of signals through a chosen path for reasons other than timing requirements. Again, the size and complexity of modern designs makes this a difficult task.